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Si570/Si571
f XTAL = ---------------------------------------------------
RFREQ new = 0x2EBB04CE0 ? --------------------------------
RFREQ new = -----------------------
A typical frequency configuration for this example:
RFREQ current = 0x2EBB04CE0
F out_current = 148.35 MHz
F out_new = 148.50 MHz
Calculate RFREQ new to change the output frequency
from 148.35 MHz to 148.5 MHz:
148.50 MHz
148.35 MHz
= 0x2EC71D666
Note: Performing calculations with RFREQ requires a mini-
mum of 38-bit arithmetic precision.
Even relatively small changes in output frequency may
require writing more than 1 RFREQ register. Such multi-
register RFREQ writes can impact the output clock
frequency on a register-by-register basis during
updating.
Interim changes to the output clock during RFREQ
writes can be prevented by using the following
procedure:
1. Freeze the “M” value (Set Register 135 bit 5 = 1).
2. Write the new frequency configuration (RFREQ).
3. Unfreeze the “M” value (Set Register 135 bit 5 = 0)
3.1.2. Reconfiguring the Output Clock for Large
Changes in Output Frequency
For output frequency changes outside of ±3500 ppm
from the center frequency, it is likely that both the DCO
frequency and the output dividers need to be
reprogrammed. Note that changing the DCO frequency
outside of the ±3500 ppm window will cause the output
to momentarily stop and restart at any arbitrary point in
a clock cycle. Devices sensitive to glitches or runt
pulses may have to be reset once reconfiguration is
complete.
The process for reconfiguring the output frequency
outside of a ±3500 ppm window first requires reading
the current RFREQ, HSDIV, and N1 values. Next,
calculate fXTAL for the device. Note that, due to slight
variations of the internal crystal frequency from one
device to another, each device may have a different
RFREQ value or possibly even different HSDIV or N1
values to maintain the same output frequency. It is
necessary to calculate fXTAL for each device. Third,
write the new values back to the device using the
appropriate registers (addresses 7–12 for all Si571
devices and Si570 devices with 20 ppm and 50 ppm
temperature stability; or addresses 13–18 for Si570
devices with 7 ppm temperature stability) sequencing as
F out ? HSDIV ? N1
RFREQ
Once f XTAL has been determined, new values for
RFREQ, HSDIV, and N1 are calculated to generate a
new output frequency (f out_new ). New values can be
calculated manually or with the Si57x-EVB software,
which provides a user-friendly application to help find
the optimum values.
The first step in manually calculating the frequency
configuration is to determine new frequency divider
values (HSDIV, N1). Given the desired output frequency
(fout_new), find the frequency divider values that will
keep the DCO oscillation frequency in the range of 4.85
to 5.67 GHz.
f DCO_new = f out_new ? HSDIV new ? N1 new
Valid values of HSDIV are 4, 5, 6, 7, 9 or 11. N1 can be
selected as 1 or any even number up to 128 (i.e. 1, 2, 4,
6, 8, 10 … 128). To help minimize the device's power
consumption, the divider values should be selected to
keep the DCO's oscillation frequency as low as
possible. The lowest value of N1 with the highest value
of HS_DIV also results in the best power savings.
Once HS_DIV and N1 have been determined, the next
step is to calculate the reference frequency multiplier
(RFREQ).
f DCO_new
f XTAL
RFREQ is programmable as a 38-bit binary fractional
frequency multiplier with the first 10 most significant bits
(MSBs) representing the integer portion of the multiplier,
and the 28 least significant bits (LSBs) representing the
fractional portion.
Before entering a fractional number into the RFREQ
register, it must be converted to a 38-bit integer using a
bitwise left shift operation by 28 bits, which effectively
multiplies RFREQ by 2 28 .
Example:
RFREQ = 46.043042064d
Multiply RFREQ by 2 28 = 12359584992.1
Discard the fractional portion = 12359584992
Convert to hexadecimal = 02E0B04CE0h
In the example above, the multiplication operation
requires 38-bit precision. If 38-bit arithmetic precision is
not available, then the fractional portion can be
separated from the integer and shifted to the left by 28-
bits. The result is concatenated with the integer portion
to form a full 38-bit word. An example of this operation is
Rev. 1.4
15
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